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EL5102, EL5103, EL5202, EL5203, EL5302
Data Sheet January 17, 2008 FN7331.8
400MHz Slew Enhanced VFAs
The EL5x02 and EL5x03 families represent high-speed VFAs based on a CFA amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. With slew rates of 3500V/s, this family of devices enables the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family will also be available in single, dual, and triple versions, with 200MHz, 400MHz, and 750MHz versions. These are all available in single, dual, and triple versions. Both families operate on single 5V or 5V supplies from minimum supply current. EL5x02 also features an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. Typical applications for these families will include cable driving, filtering, A/D and D/A buffering, multiplexing and summing within video, communications, and instrumentation designs.
Features
* Operates off 3V, 5V, or 5V applications * Power-down to 0A (EL5x02) * -3dB bandwidth = 400MHz * 0.1dB bandwidth = 50MHz * Low supply current = 5mA * Slew rate = 3500V/s * Low offset voltage = 5mV max * Output current = 140mA * AVOL = 2000 * Differential gain/phase = 0.01%/0.01 * Pb-free available (RoHS compliant)
Applications
* Video amplifiers * PCMCIA applications * A/D drivers * Line drivers * Portable computers * High speed communications * RGB applications * Broadcast equipment * Active filtering
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002-2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL5102, EL5103, EL5202, EL5203, EL5302 Ordering Information
PART NUMBER EL5102IS EL5102IS-T7* EL5102IS-T13* EL5102ISZ (Note) EL5102ISZ-T7* (Note) EL5102ISZ-T13* (Note) EL5102IW-T7* EL5102IW-T7A* EL5102IWZ-T7* (Note) EL5102IWZ-T7A* (Note) EL5103IC EL5103IC-T7* EL5103IC-T7A* EL5103IW-T7* EL5103IW-T7A* EL5103IWZ-T7* EL5103IWZ-T7A* EL5202IY EL5202IY-T7* EL5202IY-T13* EL5202IYZ (Note) EL5202IYZ-T7* (Note) EL5202IYZ-T13* (Note) EL5203IS EL5203IS-T7* EL5203IS-T13* EL5203ISZ (Note) EL5203ISZ-T7* (Note) EL5203ISZ-T13* (Note) EL5203IY EL5203IY-T7* EL5203IY-T13* EL5203IYZ (Note) EL5203IYZ-T7* (Note) EL5203IYZ-T13* (Note) EL5302IU EL5302IU-T7* EL5302IU-T13* EL5302IUZ (Note) EL5302IUZ-T7* (Note) EL5302IUZ-T13* (Note) PART MARKING 5102IS 5102IS 5102IS 5102ISZ 5102ISZ 5102ISZ q q BBSA BBSA B B B g g BBTA BBTA BRAAA BRAAA BRAAA BAAAD BAAAD BAAAD 5203IS 5203IS 5203IS 5203ISZ 5203ISZ 5203ISZ BSAAA BSAAA BSAAA BAAAE BAAAE BAAAE 5302IU 5302IU 5302IU 5302IUZ 5302IUZ 5302IUZ PACKAGE 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 (Pb-free) 6 Ld SOT-23 (Pb-free) 5 Ld SC-70 5 Ld SC-70 5 Ld SC-70 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SOT-23 (Pb-free) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 16 Ld QSOP (150 mil) 16 Ld QSOP (150 mil) 16 Ld QSOP (150 mil) 16 Ld QSOP (150 mil) (Pb-free) 16 Ld QSOP (150 mil) (Pb-free) 16 Ld QSOP (150 mil) (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0038 MDP0038 MDP0038 MDP0038 P5.049 P5.049 P5.049 MDP0038 MDP0038 MDP0038 MDP0038 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
* Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Pinouts
EL5102 (6 LD SOT-23) TOP VIEW
OUT 1 VS- 2 IN+ 3 6 VS+ 5 CE 4 INOUT 1 VS- 2 IN+ 3
EL5103 (5 LD SOT-23) TOP VIEW
5 VS+
+-
+4 IN-
EL5102 (8 LD SOIC) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC
EL5203 (8 LD SOIC, MSOP) TOP VIEW
OUTA 1 INA- 2 INA+ 3 VS- 4 + + 8 VS+ 7 OUTB 6 INB5 INB+
EL5202 (10 LD MSOP) TOP VIEW
OUT 1 IN- 2 IN+ 3 VS- 4 CE 5 + + 10 VS+ 9 OUT 8 IN7 IN+ 6 CE INA+ 1 CEA 2 VS- 3 CEB 4 INB+ 5 NC 6 CEC 7 INC+ 8
EL5302 (16 LD QSOP) TOP VIEW
16 INA+ 15 OUTA 14 VS+ + 13 OUTB 12 INB11 NC + 10 OUTC 9 INC-
3
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and GND. . . . . . . . . . . . . . . . . . 13.2V Maximum Supply Slewrate between VS+ and VS- . . . . . . . . . 1V/s Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 80mA Maximum Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . 5mA
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature Range . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VOS
VS+ = +5V, VS- = -5V, TA = +25C, RL = 500, VENABLE = +5V, Unless Otherwise Specified. CONDITIONS EL5102, EL5103, EL5202, EL5203 EL5302 MIN TYP 1 2 10 -12 -8 2 1 50 -70 -60 -3 200 -80 -80 3.3 400 1 4.6 +1 -25 58 5.2 +9 -13 66 60 3.5 3.4 80 (VS+) -5 (VS+) -1 CE = 0V CE = +5V -1 1 0 14 3.9 3.7 150 (VS+) -3 VS+ +1 25 5.8 +25 -1 3 12 8 MAX 5 8 UNIT mV mV V/C A A nA/C dB dB V k pF mA A A dB dB V V mA V V A A
DESCRIPTION Offset Voltage
TCVOS IB IOS TCIOS PSRR CMRR CMIR RIN CIN IS,ON IS,OFF
Offset Voltage Temperature Coefficient Input Bias Current Input Offset Current Input Bias Current Temperature Coefficient Power Supply Rejection Ratio Common Mode Rejection Ratio Common Mode Input Range Input Resistance Input Capacitance Supply Current - Enabled Per Amplifier
Measured from TMIN to TMAX VIN = 0V VIN = 0V Measured from TMIN to TMAX VS = 4.75V to 5.25V VCM = -3V to 3.0V Guaranteed by CMRR test Common mode SO package
Supply Current - Shut-down Per Amplifier VS+ VS-
AVOL
Open Loop Gain
VOUT = 2.5V, RL = 1k to GND VOUT = 2.5V, RL = 150 to GND
VOUT
Output Voltage Swing
RL = 1k to GND RL = 150 to GND
IOUT VCE-ON VCE-OFF IEN-ON IEN-OFF
Output Current CE Pin Voltage for Power-up CE Pin Voltage for Shut-down Pin Current - Enabled Pin Current - Disabled
AV = 1, RL = 10 to 0V
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302
Closed Loop AC Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25C, VENABLE = +5V, AV = +1, RF = 0, RL = 150 to
GND Pin, Unless Otherwise Specified. (Note 1) PARAMETER BW SR DESCRIPTION -3dB Bandwidth (VOUT = 400mVP-P) Slew Rate CONDITIONS AV = 1, RF = 0 AV = +2, RL = 100, VOUT = -3V to +3V RL = 500, VOUT = -3V to +3V tR,tF OS tS dG dP eN iN tDIS tEN NOTES: 1. All AC tests are performed on a "warmed up" part, except slew rate, which is pulse tested. 2. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. Rise Time, Fall Time Overshoot 0.1% Settling Time Differential Gain (Note 2) Differential Phase (Note 2) Input Noise Voltage Input Noise Current Disable Time (Note 3) Enable Time (Note 3) 0.1V step 0.1V step VS = 5V, RL = 500, AV = 1, VOUT = 3V AV = 2, RF = 1k AV = 2, RF = 1k f = 10kHz f = 10kHz 1100 MIN TYP 400 2200 4000 2.8 10 20 0.01 0.01 12 11 50 25 5000 MAX UNIT MHz V/s V/s ns % ns % nV/Hz pA/Hz ns ns
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M -180 -3dB BW @ 438MHz -240 10M 100M FREQUENCY (Hz) 1G 0.1 1M 10M FREQUENCY (Hz) 100M 1G VS = 5V AV = +1 RF = 0 RL = 500 CL = +3.3pF 240 180 120 PHASE () 60 0 -60 -120 VS = 5V AV = +1 RF = 0 RL = 500 CL = +3.3pF
FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH)
FIGURE 2. PHASE vs FREQUENCY
0.5 0.4 NORMALIZED GAIN (dB) 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 1M 10M FREQUENCY (Hz) 100M VS = 5V AV = +1 RF = 0 RL = 500 CL = +3.3pF
70
VS = 5V RL = 500
60 0.1dB BW @ 35MHz GAIN (dB) 50
GAIN = 40dB or 100 FREQUENCY = 1.64 MHz GAIN BW PRODUCT = 1.64 x 100 = 164MHz
40
30
20
0
1M 10M FREQUENCY (Hz)
100M
FIGURE 3. 0.1dB BANDWIDTH
FIGURE 4. GAIN BANDWIDTH PRODUCT
GAIN-BANDWIDTH PRODUCT (MHz)
300
250
NORMALIZED GAIN (dB)
VS = 5V RL = 500
5 4 3 2 1 0 -1 -2 -3 -4
VS = 5V RL = 500 CL = +3.3pF
AV = +2 RF = RG = 400 AV = +1 RF = 0
200
150
100
AV = +5 RF = 1.6k, RG = 400 0.1 1M 10M FREQUENCY (Hz) 100M 1G
50 2.0
-5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (V)
FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES
FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M 10M FREQUENCY (Hz) VS = 6 VS = 5V VS = 4V VS = 3V VS = 2.5V 100M 1G NORMALIZED GAIN (dB) AV = +1 RF = 0 RL = 500 CL = +3.3pF
(Continued)
5 4 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M RL = 150 RL = 75 RL = 50 10M FREQUENCY (Hz) 100M 1G VS = 5V AV = +1 RF = 0 CL = +3.3pF
RL = 500
RL = 1k
FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS VS
FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M 10M 100M FREQUENCY (Hz) 1G RL = 50 RL = 70 RL = 150 NORMALIZED GAIN (dB) VS = 5V AV = +2 RF = 402 CL = +3.9pF
5 4 3 2 1 0 -1 -2 -3 -4 -5 0.1 RL = 50 RL = 75 RL = 150 1M 10M FREQUENCY (Hz) 100M RL = 1k RL = 500 RL = 1k VS = 5V AV = +5 RF = 402 CL = +3.9pF
RL = 500
FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2)
FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +5)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5
NORMALIZED GAIN (dB)
VS = 5V AV = +1 RF = 0 RL = 500
5 CL = 15pF CL = 8.2pF CL = 27pF 4 3 2 1 0 -1 -2 -3 -4 -5 1G
VS = 5V AV = +2 RF = 400 RL = 500
CL = 33pF CL = 18pF
CL = 47pF
CL = 3.3pF CL = 0pF 0.1 1M 10M FREQUENCY (Hz) 100M
CL = 8.2pF CL = 0pF 0.1 1M 10M 100M FREQUENCY (Hz) 1G
FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +1)
FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2)
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M 10M 100M FREQUENCY (Hz) CL = 0pF CL = 56pF NORMALIZED GAIN (dB) VS = 5V AV = +5 RF = 400 RL = 500 CL = 150pF CL = 100pF CL = 220pF
(Continued)
5 4 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M 10M 100M 1G FREQUENCY (Hz) RF = 50 RF = 25 RF = 0 VS = 5V AV = +1 RL = 500 CL = +3pF RF = 150
RF = 100
FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +5)
FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +1)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5
NORMALIZED GAIN (dB)
VS = 5V AV = +2 RL = 500 CL = +8pF
5 RF = 1.0k RF = 680 4 3 2 1 0 -1 -2 -3 -4 100M 1G -5
VS = 5V AV = +5 RL = 500 CL = +12pF
RF = 4k RF = 2k
RF = 402 RF = 274 RF = 100 0.1 1M 10M FREQUENCY (MHz)
RF = 100 RF = 1k RF = 402 0.1 1M 10M 100M
FREQUENCY (Hz)
FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2)
FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5)
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 0.1 1M CIN = 1pF VS = 5V CIN = 3.3pF AV = +2 RF = RG = 402 CIN = 2.2pF RL = 500 CL= +8pF
CIN = 4.7pF NORMALIZED GAIN (dB)
5 4 3 2 1 0 -1 -2 -3 -4 CIN = 0pF CIN = 4.7pF VS = 5V AV = +5 RG = 402 RL = 1600 CL = +12pF CIN = 8.2pF CIN = 10pF CIN = 6.8pF
CIN = 0pF 10M 100M FREQUENCY (Hz) 1G
-5
0.1
1M 10M FREQUENCY (Hz)
100M
FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2)
FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5)
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
80 70 60 50 GAIN (dB) 40 30 20 10 0 -10 -20 10 VCC = +5V VEE = -5V 100 1k 10k 100k 1M GAIN PHASE
(Continued)
-45 0 45 90 135 180 225 270 315 360 PHASE () OUTPUT IMPEDANCE () 100 10 AV = +2 VS = 5V
1
0.1
0.01 10k 100k 1M FREQUENCY (Hz) 10M 100M
405 10M 100M 1G
FREQUENCY (Hz)
FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY
FIGURE 20. OUTPUT IMPEDANCE/PHASE vs FREQUENCY
-10 -20 -30 CMRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 1k
AV = +5 VS = 5V
10 0 -10 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 -90 1k
AV = +1 VS = 5V
+PSRR -PSRR 10k 100k 1M 10M 100M 500M
10k
100k
1M
10M
100M 500M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 21. CMRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
MAX OUTPUT VOLTAGE SWING (VP-P)
10 9 8 7 6 5 4 3 2 1 0 VS = 5V AV = +2 RF = RG = 402 CL = 8pF 0.1 1M RLOAD = 1k GROUP DELAY (ns) RLOAD = 150
10M FREQUENCY (Hz)
100M
1G
30 25 VS = 5V A = +1 20 RV = 0 F 15 RL = 500 10 5 0 -5 -10 -15 -20 -25 -30 0.1 1M
10M 100M FREQUENCY (Hz)
1G
FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 24. GROUP DELAY vs FREQUENCY
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
-10 -20 -30 ISOLATION (dB) -40 -50 -60 -70 -80 -90 -100 0.1 1M 10M FREQUENCY (Hz) 100M 1G INPUT TO OUTPUT VS = 5V AV = +1 RF = 0 CHIP DISABLED OUTPUT TO INPUT
(Continued)
10 NOTE: 0 VS = 5V This was done on the -10 AV = +1 EL5203 (Dual Op-Amps) RF = 0 -20 RL = 500 -30 BIN TO AOUT -40 -50 AIN TO BOUT -60 -70 -80 -90 -100 -110 -120 0.1 1M 10M 100M FREQUENCY (Hz)
GAIN (dB)
1G
FIGURE 25. INPUT AND OUTPUT ISOLATION
FIGURE 26. CHANNEL-TO-CHANNEL ISOLATION
-30 HARMONIC DISTORTION (dBc) -40 -50 -60 -70 -80 -90 -100 0.1 3rd HD 1M 10M FUNDAMENTAL FREQUENCY (Hz) 100M VS = 5V AV = +1 RF = 0 RL = 500 CL = 3.3pF VOUT = 2VP-P
-20 -30 -40 T.H.D 2nd HD THD (dBc) -50 -60 -70 -80 -90 -100 0
VS = 5V AV = +5 RG = 402 RF = 1600 RL = 500 CL = 12pF
FIN = 10MHz
FIN = 1MHz 1 2 3 4 5 6 7 8
OUTPUT VOLTAGES (VP-P)
FIGURE 27. HARMONIC DISTORTION vs FREQUENCY
FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES
6 5 4 AMPLITUDE (V) 3 2 1 0 -1 -2 -3 -600 -400 -200 ENABLE SIGNAL
AMPLITUDE (V)
VS = 5V AV = +1 RF = 0 RL = 500 VOUT = 2VP-P
6
VS = 5V 5 AV = +1 RF = 0 4 R = 500 L 3 VOUT = 2VP-P 2 1 0 -1 -2
DISABLE SIGNAL OUTPUT SIGNAL
OUTPUT SIGNAL
0 200 400 600 800 1000 1200 1400 1600 TIME (ns)
-3 -600 -400 -200 0
200 400 600 800 1000 1200 1400 1600 TIME (ns)
FIGURE 29. TURN-ON TIME
FIGURE 30. TURN-OFF TIME
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
1000 VS = 5V NOISE VOLTAGE (nV/Hz)
(Continued)
0.5 VS = 5V 0.4 AV = +1 RF = 0 0.3 AMPLITUDE (V) 0.2 0.1 0.0 -0.1 -0.2 tRISE = 0.923ns tFALL = 0.9ns RL = 500 CL = 3.3pF VOUT = 400mV
100
10
1 10
100
1k FREQUENCY (Hz)
10k
100k
-0.3 -20
0
20
40
60 80 100 120 140 160 TIME (ns)
FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY
FIGURE 32. SMALL SIGNAL STEP RESPONSE RISE AND FALL TIME
5 4 AMPLITUDE (V) 3 2 1 0 -1 -2 -3 -20 0 20 40 60 80 100 120 140 160 TIME (ns) tFALL = 1.167ns tRISE = 1.243ns SUPPLY CURRENT (mA) VS = 5V AV = +5 RG = 25 RL = 500 CL = 5pF VOUT = 4.0V
6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2
AV = +1 RF = 0 RL = 500 CL = 3.3pF
Please note that the curve showed positive Current. The negative current was almost the same. 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 5.5 6.0
4.0 2.5
FIGURE 33. LARGE SIGNAL STEP RESPONSE RISE AND FALL TIME
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
10 0 -10 AMPLITUDE (dBm) -20 -30 -40 -50
IP3 (dBm)
VS = 5V AV = +5 RF = 1600 RL = 100 CL = 12pF f1 = 1dBm @ 0.95MHz
IM = (1) - (-77) = 78dB IP3 = 1+ (78/2) = 40dBm f2 = 1dBm @ 1.05MHz
50 45 40 35 30 25 20 15 10 5 0
VS = 5V AV = +5 RF = 1600 RL = 100 CL = 12pF
2f1-f2 = -76.8dBm -60 @ 0.85MHz -70 -80 -90 -100 0.8M
2f2-f1 = -77.0dBm @ 1.15MHz
0.9M 1.0M FREQUENCY (Hz)
1.1M
1.2M
1M
10M FREQUENCY (Hz)
100M
FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3)
FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY
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FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves
1.2 POWER DISSIPATION (W)
M
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) 1.2 1.136W 1.0 1.116W 0.8 0.6 0.4 0.2 0 SO8 JA = +110C/W
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.0 1.087W 0.8 0.6 543mW 0.4 0.2 0 0 25
JA =
P8 /1 +1 0 15 C /W
T2 3 - 5/6 230 C/ W
SO
J
SO
QSOP16 JA = +112C/W
A =+
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.7 607mW POWER DISSIPATION (W) 488mW MSOP8/10 JA = +206C/W POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +256C/W 0.8 0.6 0.4 0.2 0 1.0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
791mW 781mW QSOP16 JA = +158C/W
SO8 JA = +160C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
12
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
13
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
14
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
15
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 5 0.25 Rev. 3 7/07 NOTES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053
5 E 1 2 3
4 C L C L E1
A1 A2 b b1 c c1
C
e
C L 0.20 (0.008) M C L C
b
D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o
0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 8o
0.10 (0.004) C
L2
WITH PLATING c
b b1 c1
N R R1 NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C 0.4mm L1
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
0.75mm
2.1mm
0.65mm TYPICAL RECOMMENDED LAND PATTERN
16
FN7331.8 January 17, 2008
EL5102, EL5103, EL5202, EL5203, EL5302 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 17
FN7331.8 January 17, 2008

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